1. Field of the Invention
The present invention relates to a decoder circuit for a storage module having storage cells constructed from MOS transistors which are arranged between word and bit lines, and more particularly to such a decoder circuit in which, for the selection of one of the word lines or bit lines, the control inputs of the decoder transistors are fed with n address signals in negated or non-negated form and a decoder output signal is emitted on a decoder output line which connects terminals of the controlled paths of the decoder transistors.
2. Description of the Prior Art
Decoder circuits for storage modules in which the storage cells consist of MOS transistors are arranged between word lines and bit lines as is known, for example, from the IBM Technical Disclosure Bulletin, Vol. 12, No. 13, May 1970, Page 2082. In this publication, a decoder circuit is provided for each bit line and word line. The decoder circuit consists of MOS transistors whose control paths are arranged parallel to one another. In the following, these MOS transistors will be referred to as decoder transistors. The control inputs of these decoder transistors are fed with address signals in non-negated form or in negated form. The one electrodes of the controlled paths of the decoder transistors are connected to one another and form a so-called decoder output line, which generally is connected to an output amplifier which leads to the bit line and word line of the storage module. The other electrodes of the controlled paths of the decoder transistors are likewise connected to one another and then connected to an operating voltage. The mode of operation of such a known decoder circuit is well known in the art and will not be discussed further hereinbelow.
Conventionally, the decoder circuits are integrated, together with the storage cells of a storage module. Therefore, a problem exists in designing the decoder circuits so that they assume a space on the storage module which is as small as possible. To this end, it is known to arrange the decoder transistors on the semiconductor module in parallel to the address lines, whereas the decoder output lines and the lines for the operating voltage are arranged at right angles to the address lines. In this case, the address lines are metal lines, whereas the decoder output lines and the line for the operating voltage are diffused into the semiconductor module. A disadvantage of such an arrangement resides in the fact that the decoder grid formed from the decoder output line to the line for the operating voltage is relatively large.
It is also known to arrange the decoder transistors in parallel to the decoder output lines, whereas the address lines are arranged at right angles to the decoder output lines. In this case, two address lines are, in each case, followed by a line for the operating voltage. Here, the address lines are in the form of silicon address lines. In this embodiment, the decoder grid is smaller than in the previously described situation, although the height of the decoder circuit, which corresponds approximately to the length of the decoder output line, is larger.